A parallel algorithm synthesis procedure for high-performance computer architectures (Record no. 6727)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 00474nam a2200145Ia 4500 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 211224s9999 xx 000 0 und d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 306477432 |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 005.275 DUN |
| 100 ## - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Dunn, Ian N |
| 245 #2 - TITLE STATEMENT | |
| Title | A parallel algorithm synthesis procedure for high-performance computer architectures |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. | |
| Place of publication, distribution, etc. | New York: |
| Name of publisher, distributor, etc. | Kluwer Academic/Plenum Publishers, |
| Date of publication, distribution, etc. | 2003 |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | xi, 108 p. : ill. ; 24 cm. |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Computer architecture |
| 700 ## - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Meyer, Gerard G. L |
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